FFT IP Core 8.1

I got the FFT 8.1 working with the Nios II!!!!

First of all, the OPTIONAL signal clockenable is not optional. If you do not add it via the Wizard and apply a fixed value of 1(high) to it, the generated IP-core will not behave like in the simulation. In my case the IP-core only accepted 7 times 32bit and than de-asserted the ready signal until it was reset.

I used a 1024points FFT with 16bit data width, Burst Architecture, a Single Output and "Add ClockEnable" checked. I wrote a wrapper around the created IP-core including two FIFOs and some status and control registers. The two 16bit inputs and outputs are merged. The 6bit Exponent Output which is required for scaling the results is readable via an additional Avalon-MM-slave Port.

I spend more than 14 days on this problem, because of the documantation of Altera...