FFT IP Core 8.1

Hi,

I also tried using another module to control my FFT, still the same prob. FFT never even starts the SOP for the output. I am really stuck. Plz help.

All the proj files are attached.

K guys

Sort of figured it out.

1) FFT core in 8p1 doesnt work (for me atleast). the controller i wrote worked for 7.2 where as no output for 8.1.

2) still getting source_error but it is code 2 this time and also at the same time output of FFT is there. error occurs after end of packets but output is valid in the packets.

may be som1 will find the right way to handle fft on quartus 8.1

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Hi,

I m using FFT IP core for the first time. i have spent several hours and experimented on different size andn types of FFT Functions using startix II. I still cant get EOP right while using waveform simulation. i.e. in case of 64 points, i have tried a gap of 62,63,64 cycles between sop and eop but still i m getting source error 3(When EOP is asserted before N valid samples are accepted). There should be a point (far far away from sop) where if i insert EOP, i should get error 2 ("Missing EOP" is asserted if the FFT accepts N valid samples of an FFT frame, but it is not completed with an EOP signal.) but this error never occours. I m using 40ns clock time period and i have tried EOP at the end simulation uptil 20 usec. Still error code 3.

FFT user guide suggests that sink ready should be asserted high (which is an output). if i assert this signal high, FFT sets it to low after first SOP and it never gets high again. I am attaching both input and output vwf files.

ANY HELP WILL BE HIGHLY APPRICIATED.

Regards

Omar

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i have similar pro.:confused:

Would someone help me?

This FFT is really unpredictable. The cntroller which works for me in uni, doesnt work when i use it at home. however i'll attach the controller which works with quartus 7.2 (most of the time though). genrate a symbol file for this controller and assert the sink ready and reset high in BDF file. Use the BDF file to provide inputs and monitor outputs. this is a 1024 point FFT controller with 16 bits. It instanciates the megacore genrated FFT named "FFT", so change the name if u use a diff name.

good luck

regards

Omar Anwar

Salaam Omar,

I'm also having some trouble with FFT v8.0, although in my case I think I am talking to the FFT block correctly, but I'm getting unexpected results. In my case I'm using a Nios processor, but you might be able to get the protocol information by looking at my code. Have a look at my post here (http://www.alteraforum.com/forum/showthread.php?t=4200). We might be able to help each other.

--Amr

Sorry AMR,

i wish i could help you but i am not using NIOS. But my best guess would be that the ausio codec of yours is not working properly. thats y, u get nothing at PC.

Good luck

Omar

Hi,

I'm testing FFT mega core v8.1 with Quartus waveform simulator and i'm not getting any results in the output, which is always 0. Can anyone help me understand what is happening??

Thank you.

Duarte Carona

Go for altera 7.2 because 8.0 or 8.1 didnt work for me either.

also try n write a controller (to provide all the control signals with accurate timing) to test the FFT Core and plot its output and input in waveform simulator. Waveform simulator inputs wont help u as accurate input timings are very hard to implement in waveform.

Best of Luck

Well, for simulation u will have to use garbage values. if u are getting output start of frame(s) and end of frame(s) at proper locations along with other valid signals, purpose of simulation is achieved. For testing on FPGA, you will have to use either a MIF or HEX file to initialize memory with proper data. Or u can use analog audio input (if it is on ur board) to provide data at run time but this is bit tricky coz of audio codec issues.

Good Luck