New ContributorFFT Intel FPGA IP (altera_fft_ii) unexpected source error (missing sop)
Dear Intel FPGA community members,
I am getting a strange error from the Intel FFT FPGA IP. The waveform from Signal Tap Logic analyzer is below:
I am raising the sink_valid and sink_sop at the same cycle and sink_sop take 1 cycle and valid stays high. after 4 cycles I get the source_error=1 and source_eop pulsed and nothing comes out afterwards from the module.
I am using a time_limited ip at the moment but this happens just after I download the sof file and run my application. I hope this is not related to ip evaluation mode.
design is running at 250 MHz clock and there is a top level constraint for the clock tree.
I create the fft module with tcl script below and instantiate it in my hierarchy.
What could be possible reason for such a behavior?
I would appreciate if you can help me solving this issue.
package require qsys # create the system "fft_ip" proc do_create_fft_ip {} { # create the system create_system fft_ip set_project_property DEVICE {10AX016E3F27I2SG} set_project_property DEVICE_FAMILY {Arria 10} set_project_property HIDE_FROM_IP_CATALOG {true} set_use_testbench_naming_pattern 0 {} # add the components add_instance fft_ii_0 altera_fft_ii 19.1 set_instance_parameter_value fft_ii_0 {data_flow} {Streaming} set_instance_parameter_value fft_ii_0 {data_rep} {Block Floating Point} set_instance_parameter_value fft_ii_0 {design_env} {NATIVE} set_instance_parameter_value fft_ii_0 {direction} {Bi-directional} set_instance_parameter_value fft_ii_0 {dsp_resource_opt} {0} set_instance_parameter_value fft_ii_0 {engine_arch} {Quad Output} set_instance_parameter_value fft_ii_0 {hard_fp} {0} set_instance_parameter_value fft_ii_0 {hyper_opt} {0} set_instance_parameter_value fft_ii_0 {in_order} {Natural} set_instance_parameter_value fft_ii_0 {in_width} {16} set_instance_parameter_value fft_ii_0 {length} {8192} set_instance_parameter_value fft_ii_0 {num_engines} {4} set_instance_parameter_value fft_ii_0 {out_order} {Natural} set_instance_parameter_value fft_ii_0 {out_width} {29} set_instance_parameter_value fft_ii_0 {twid_width} {16} set_instance_property fft_ii_0 AUTO_EXPORT true # add wirelevel expressions # add the exports set_interface_property clk EXPORT_OF fft_ii_0.clk set_interface_property rst EXPORT_OF fft_ii_0.rst set_interface_property sink EXPORT_OF fft_ii_0.sink set_interface_property source EXPORT_OF fft_ii_0.source # set the the module properties set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?> <bonusData> <element __value="fft_ii_0"> <datum __value="_sortIndex" value="0" type="int" /> </element> </bonusData> } set_module_property FILE {fft_ip.ip} set_module_property GENERATION_ID {0x00000000} set_module_property NAME {fft_ip} # save the system sync_sysinfo_parameters save_system fft_ip } # create all the systems, from bottom up do_create_fft_ip
