Occasional ContributorF-tile transceiver IP simulation
Hello Intel FPGA forum,
I am attempting to simulate the F-tile Architecture and PMA and FEC Direct PHY IP core. I have generated RX and TX simplex IPs, as well as the F-Tile Reference and System PLL Clocks Intel FPGA IP.
I created a simple testbench to instantiate these components, and generated the simulation script in Quartus 22.4. I loaded all this into mentor's Questasim, but the IP cores aren't doing anything. I've attached a screenshot from Questasim, showing the ports of the IP cores.
In the TX and RX IP cores, the '?x_rst_ack' signals are never asserted, no matter how long I assert the '?x_rst' signals (I've asserted for up to 1000us)
Additionally, the outputs of the Reference and System PLL Clocks are fixed at '1'.
Is there something I need to do to make the F-Tile Reference and System PLL Clocks IP work?
Thank you for your assistance.
Kind regards,
Sam de Jong
Hi Sir
I have checked the user guide, out_systempll_clk_ and out_refclk_fgt_ ports are not supported for simulation, and there is no current plan to support this.
There is a small note that mentioned this in the User Guide (page 110 and 222):
"Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel FPGA IP. These ports cannot be simulated."
PDF link to this user guide: https://cdrdv2.intel.com/v1/dl/getContent/683872
The understanding is that the System PLL outputs are not visible in simulation, but they are operating "under the hood". This would explain F-Tile PHY functionality even though the System PLL *appears* to not be functional in simulation.
