Forum Discussion
Occasional ContributorF-tile transceiver IP simulation
Hi Sir
I have checked the user guide, out_systempll_clk_ and out_refclk_fgt_ ports are not supported for simulation, and there is no current plan to support this.
There is a small note that mentioned this in the User Guide (page 110 and 222):
"Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel FPGA IP. These ports cannot be simulated."
PDF link to this user guide: https://cdrdv2.intel.com/v1/dl/getContent/683872
The understanding is that the System PLL outputs are not visible in simulation, but they are operating "under the hood". This would explain F-Tile PHY functionality even though the System PLL *appears* to not be functional in simulation.
ContributorHi
For F-Tile PMA/FEC Direct PHY simulation, you can refer to the 'F-tile Architecture and PMA and FEC Direct PHY IP User Guide', see section "6.7. Simulating the F-Tile PMA/FEC Direct PHY Design"
PDG User Guide link: https://cdrdv2.intel.com/v1/dl/getContent/683872
Occasional ContributorHi skbeh,system
Thank you for replying. I followed the instruction in that document when I initially tried to setup the simulation, and what I showed was the result of that. The ports Reference and System PLL Clocks IP never changes.
