Forum Discussion
Occasional ContributorF-tile transceiver IP simulation
Hi Sir
I have checked the user guide, out_systempll_clk_ and out_refclk_fgt_ ports are not supported for simulation, and there is no current plan to support this.
There is a small note that mentioned this in the User Guide (page 110 and 222):
"Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel FPGA IP. These ports cannot be simulated."
PDF link to this user guide: https://cdrdv2.intel.com/v1/dl/getContent/683872
The understanding is that the System PLL outputs are not visible in simulation, but they are operating "under the hood". This would explain F-Tile PHY functionality even though the System PLL *appears* to not be functional in simulation.
ContributorHi Sir
Please refer to the attached the .zip, ppt, and .wlf files of a functional simulation design for your reference.
Also, refer to the .ppt (page# 36) that include the steps on how to run the simulation.
The System PLL is not supported in simulation, so the System PLL output ports will not toggling in simulation. These ports are however functioning under the hood which is evident from the F-tile Direct PHY IP functioning in simulation. The design is with Soft PRBS with RSFEC Demo Design (FGT mode) which also can be found here https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Agilex-I-Series-F-Tile/ta-p/1315123.
Please note that the simulation takes many hours to complete.
