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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

F-tile transceiver IP simulation

Hello Intel FPGA forum, I am attempting to simulate the F-tile Architecture and PMA and FEC Direct PHY IP core. I have generated RX and TX simplex IPs, as well as the F-Tile Reference and System P...
  • skbeh's avatar
    skbeh
    3 years ago

    Hi Sir

    I have checked the user guide, out_systempll_clk_ and out_refclk_fgt_ ports are not supported for simulation, and there is no current plan to support this.


    There is a small note that mentioned this in the User Guide (page 110 and 222):

    "Ports ending in "_link" must connect to the F-Tile Reference and System PLL Clocks Intel FPGA IP. These ports cannot be simulated."

    PDF link to this user guide: https://cdrdv2.intel.com/v1/dl/getContent/683872


    The understanding is that the System PLL outputs are not visible in simulation, but they are operating "under the hood". This would explain F-Tile PHY functionality even though the System PLL *appears* to not be functional in simulation.


SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

For others that came across this problem, the solution that worked (which I discovered through the example designs provided) is:

  1. In quartus, run the 'Logic Generation' option in 'Project Overview'
    • This will generate a directory called 'support logic'
  2. Run 'Generate Simulator script for IP'
  3. In your testbench, add this entity declaration:
    • <top-level-entity-name>_auto_tiles_inst : entity <top-level-entity-name>_auto_tiles.<top-level-entity-name>_auto_tiles;
    • There are no ports on this entity
    • This entity is declared in 'support_logic/<top-level-entity-name>_auto_tiles.sv'
    • 'mentor/Modelsim.ini' loads this entity into memory
  4. Add the top level with it's own name as the entity label:
    • e.g., <top-level-entity-name>: entity work.<top-level-entity-name>
  5. Now you can run the simulation.