Error(14530): pce_tx[0] is locked to a non-HIP location. The HIP locations are G22 G22 G22 G22 G22

Question

I tried to move the project from 10cx220YF780E5G to 10CX220YU484I5G.
                    Bank   Pair                       Bank   Pair
pce_rx[0]    Input  PIN_V26      1C     pce_rx[0](n) PIN_V26             PIN_Y20      1C       pce_rx[0](n)
pce_rx[0](n) Input        1C     pce_rx[0]    PIN_V25             PIN_Y19      1C     pce_rx[0]
pce_rx[1]    Input  PIN_T26      1C     pce_rx[1](n) PIN_T26             PIN_U22      1C       pce_rx[1](n)
pce_rx[1](n) Input        1C     pce_rx[1]    PIN_T25             PIN_U21      1C     pce_rx[1]
pce_rx[2]    Input  PIN_P26      1D     pce_rx[2](n) PIN_P26             PIN_N22      1C       pce_rx[2](n)
pce_rx[2](n) Input        1D     pce_rx[2]    PIN_P25             PIN_N21      1C     pce_rx[2]
pce_rx[3]    Input  PIN_M26      1D     pce_rx[3](n) PIN_M26             PIN_J22      1C       pce_rx[3](n)
pce_rx[3](n) Input        1D     pce_rx[3]    PIN_M25             PIN_J21      1C     pce_rx[3]
pce_tx[0]    Output PIN_W28      1C     pce_tx[0](n) PIN_W28             PIN_AA22 1C  pce_tx[0](n)
pce_tx[0](n) Output       1C     pce_tx[0]    PIN_W27             PIN_AA21 1C  pce_tx[0]
pce_tx[1]    Output PIN_U28      1C     pce_tx[1](n) PIN_U28             PIN_W22      1C       pce_tx[1](n)
pce_tx[1](n) Output       1C     pce_tx[1]    PIN_U27             PIN_W21      1C     pce_tx[1]
pce_tx[2]    Output PIN_R28      1D     pce_tx[2](n) PIN_R28             PIN_R22      1C       pce_tx[2](n)
pce_tx[2](n) Output       1D     pce_tx[2]    PIN_R27             PIN_R21      1C     pce_tx[2]
pce_tx[3]    Output PIN_N28      1D     pce_tx[3](n) PIN_N28             PIN_L22      1C       pce_tx[3](n)
pce_tx[3](n) Output       1D     pce_tx[3]    PIN_N27             PIN_L21      1C     pce_tx[3]
Error(14530): pce_tx[0] is locked to a non-HIP location. The HIP locations are  G22 G22 G22 G22 G22 G22.
A very strange list for selecting pins. Maybe a Quartus error?

sengkok_l_intel · Answer

Hi,

The 10CX220YU484I5G only has 1 PCIe HIP, you may try to remove the PCIe pins assignment and let Quartus auto-assign for you, and then you can check the pin assignment location from the fitter report.

Regards -SK

vadimk · Answer

Thank you for your responsiveness!
I removed the pin assignments:

Node Name
Direction
Location
I/O Bank
I/O standart
Dif Pair

pce_rx[3]
Input

Current Mode Logic (CML)
pce_rx[3](n)

pce_rx[3](n)
Input

Current Mode Logic (CML)
pce_rx[3]

pce_rx[2]
Input

Current Mode Logic (CML)
pce_rx[2](n)

pce_rx[2](n)
Input

Current Mode Logic (CML)
pce_rx[2]

pce_rx[1]
Input

Current Mode Logic (CML)
pce_rx[1](n)

pce_rx[1](n)
Input

Current Mode Logic (CML)
pce_rx[1]

pce_rx[0]
Input

Current Mode Logic (CML)
pce_rx[0](n)

pce_rx[0](n)
Input

Current Mode Logic (CML)
pce_rx[0]

pce_tx[3]
Output

High Speed Differential I/O
pce_tx[3](n)

pce_tx[3](n)
Output

High Speed Differential I/O
pce_tx[3]

pce_tx[2]
Output

High Speed Differential I/O
pce_tx[2](n)

pce_tx[2](n)
Output

High Speed Differential I/O
pce_tx[2]

pce_tx[1]
Output

High Speed Differential I/O
pce_tx[1](n)

pce_tx[1](n)
Output

High Speed Differential I/O
pce_tx[1]

pce_tx[0]
Output

High Speed Differential I/O
pce_tx[0](n)

pce_tx[0](n)
Output

High Speed Differential I/O
pce_tx[0]

pcie_perstn
Input

1.8 V

pcie_refclk
Input

Current Mode Logic (CML)
pcie_refclk(n)

pcie_refclk(n)
Input

Current Mode Logic (CML)
pcie_refclk

Now it gives this error:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_GEN3_X8_PCIE_HIP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error(175001): The Fitter cannot place 1 HSSI_GEN3_X8_PCIE_HIP, which is within Intel Arria 10/Cyclone 10 Hard IP for PCI Express top_pcie_a10_hip_0_altera_pcie_a10_hip_181_nzarq7q. Info(14596): Information about the failing component(s): Info(175028): The HSSI_GEN3_X8_PCIE_HIP name(s): conv3x3_coprocessor_i|top_hw_i|pcie_a10_hip_0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error(175006): There is no routing connectivity between the HSSI_GEN3_X8_PCIE_HIP and destination HSSI_RX_PLD_PCS_INTERFACE Info(175027): Destination: HSSI_RX_PLD_PCS_INTERFACE conv3x3_coprocessor_i|top_hw_i|pcie_a10_hip_0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g2x4.phy_g2x4|phy_g2x4|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface Error(175022): The HSSI_GEN3_X8_PCIE_HIP could not be placed in any location to satisfy its connectivity requirements Error(175022): The HSSI_RX_PLD_PCS_INTERFACE could not be placed in any location to satisfy its connectivity requirements Info(175029): 1 location affected Info(175029): HSSIGEN3X8PCIEHIP_L0 
*.rpt files are not generated.
What should I do now?

sengkok_l_intel · Answer

I found that you are using the C10 u484 package, please refer to the notes in the product table below, this package only supports 2 lanes of PCIe. Please change your design to Gen2/1x2.

https://www.intel.la/content/dam/www/programmable/us/en/pdfs/literature/pt/cyclone-10-gx-product-table.pdf

vadimk · Answer

Thanks for the tip!
Do I understand correctly that only such connection to contacts is possible?

pce_rx[1]
PIN_A20

pce_rx[0]
PIN_E22

pce_rx[1](n)
PIN_A19

pce_rx[0](n)
PIN_E21

pce_tx[1]
PIN_C22

pce_tx[0]
PIN_G22

pce_tx[0](n)
PIN_G21

pce_tx[1](n)
PIN_C21

It turns out that it is impossible to connect tx0 to AA22?
Constantly writes: "Hip locations-G22 G22 G22 G.."
After all, we have already made a printed circuit board.

sengkok_l_intel · Answer

Apparently, channel 0 of PCIe is started at G22. This is the hard block, so their location is unable to change.

Forum Discussion

Error(14530): pce_tx[0] is locked to a non-HIP location. The HIP locations are G22 G22 G22 G22 G22

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Node Name	Direction	Location	I/O Bank	I/O standart	Dif Pair
pce_rx[3]	Input			Current Mode Logic (CML)	pce_rx[3](n)
pce_rx[3](n)	Input			Current Mode Logic (CML)	pce_rx[3]
pce_rx[2]	Input			Current Mode Logic (CML)	pce_rx[2](n)
pce_rx[2](n)	Input			Current Mode Logic (CML)	pce_rx[2]
pce_rx[1]	Input			Current Mode Logic (CML)	pce_rx[1](n)
pce_rx[1](n)	Input			Current Mode Logic (CML)	pce_rx[1]
pce_rx[0]	Input			Current Mode Logic (CML)	pce_rx[0](n)
pce_rx[0](n)	Input			Current Mode Logic (CML)	pce_rx[0]
pce_tx[3]	Output			High Speed Differential I/O	pce_tx[3](n)
pce_tx[3](n)	Output			High Speed Differential I/O	pce_tx[3]
pce_tx[2]	Output			High Speed Differential I/O	pce_tx[2](n)
pce_tx[2](n)	Output			High Speed Differential I/O	pce_tx[2]
pce_tx[1]	Output			High Speed Differential I/O	pce_tx[1](n)
pce_tx[1](n)	Output			High Speed Differential I/O	pce_tx[1]
pce_tx[0]	Output			High Speed Differential I/O	pce_tx[0](n)
pce_tx[0](n)	Output			High Speed Differential I/O	pce_tx[0]
pcie_perstn	Input			1.8 V
pcie_refclk	Input			Current Mode Logic (CML)	pcie_refclk(n)
pcie_refclk(n)	Input			Current Mode Logic (CML)	pcie_refclk

pce_rx[1]	PIN_A20
pce_rx[0]	PIN_E22
pce_rx[1](n)	PIN_A19
pce_rx[0](n)	PIN_E21
pce_tx[1]	PIN_C22
pce_tx[0]	PIN_G22
pce_tx[0](n)	PIN_G21
pce_tx[1](n)	PIN_C21