Forum Discussion
VadimK
New Contributor
New ContributorError(14530): pce_tx[0] is locked to a non-HIP location. The HIP locations are G22 G22 G22 G22 G22
I tried to move the project from 10cx220YF780E5G to 10CX220YU484I5G.
Bank Pair Bank Pair
pce_rx[0] Input PIN_V26 1C pce_rx[0](n) PIN_V26...
SengKok_L_Intel
Regular Contributor
Regular ContributorI found that you are using the C10 u484 package, please refer to the notes in the product table below, this package only supports 2 lanes of PCIe. Please change your design to Gen2/1x2.
VadimKNew Contributor
New ContributorThanks for the tip!
Do I understand correctly that only such connection to contacts is possible?
| pce_rx[1] | PIN_A20 |
| pce_rx[0] | PIN_E22 |
| pce_rx[1](n) | PIN_A19 |
| pce_rx[0](n) | PIN_E21 |
| pce_tx[1] | PIN_C22 |
| pce_tx[0] | PIN_G22 |
| pce_tx[0](n) | PIN_G21 |
| pce_tx[1](n) | PIN_C21 |
It turns out that it is impossible to connect tx0 to AA22?
Constantly writes: "Hip locations-G22 G22 G22 G.."
After all, we have already made a printed circuit board.
