New Contributor
Regular ContributorHi,
The 10CX220YU484I5G only has 1 PCIe HIP, you may try to remove the PCIe pins assignment and let Quartus auto-assign for you, and then you can check the pin assignment location from the fitter report.
Regards -SK
New ContributorThank you for your responsiveness!
I removed the pin assignments:
| Node Name | Direction | Location | I/O Bank | I/O standart | Dif Pair |
| pce_rx[3] | Input | Current Mode Logic (CML) | pce_rx[3](n) | ||
| pce_rx[3](n) | Input | Current Mode Logic (CML) | pce_rx[3] | ||
| pce_rx[2] | Input | Current Mode Logic (CML) | pce_rx[2](n) | ||
| pce_rx[2](n) | Input | Current Mode Logic (CML) | pce_rx[2] | ||
| pce_rx[1] | Input | Current Mode Logic (CML) | pce_rx[1](n) | ||
| pce_rx[1](n) | Input | Current Mode Logic (CML) | pce_rx[1] | ||
| pce_rx[0] | Input | Current Mode Logic (CML) | pce_rx[0](n) | ||
| pce_rx[0](n) | Input | Current Mode Logic (CML) | pce_rx[0] | ||
| pce_tx[3] | Output | High Speed Differential I/O | pce_tx[3](n) | ||
| pce_tx[3](n) | Output | High Speed Differential I/O | pce_tx[3] | ||
| pce_tx[2] | Output | High Speed Differential I/O | pce_tx[2](n) | ||
| pce_tx[2](n) | Output | High Speed Differential I/O | pce_tx[2] | ||
| pce_tx[1] | Output | High Speed Differential I/O | pce_tx[1](n) | ||
| pce_tx[1](n) | Output | High Speed Differential I/O | pce_tx[1] | ||
| pce_tx[0] | Output | High Speed Differential I/O | pce_tx[0](n) | ||
| pce_tx[0](n) | Output | High Speed Differential I/O | pce_tx[0] | ||
| pcie_perstn | Input | 1.8 V | |||
| pcie_refclk | Input | Current Mode Logic (CML) | pcie_refclk(n) | ||
| pcie_refclk(n) | Input | Current Mode Logic (CML) | pcie_refclk |
Now it gives this error:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_GEN3_X8_PCIE_HIP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 HSSI_GEN3_X8_PCIE_HIP, which is within Intel Arria 10/Cyclone 10 Hard IP for PCI Express top_pcie_a10_hip_0_altera_pcie_a10_hip_181_nzarq7q.
Info(14596): Information about the failing component(s):
Info(175028): The HSSI_GEN3_X8_PCIE_HIP name(s): conv3x3_coprocessor_i|top_hw_i|pcie_a10_hip_0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between the HSSI_GEN3_X8_PCIE_HIP and destination HSSI_RX_PLD_PCS_INTERFACE
Info(175027): Destination: HSSI_RX_PLD_PCS_INTERFACE conv3x3_coprocessor_i|top_hw_i|pcie_a10_hip_0|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g2x4.phy_g2x4|phy_g2x4|g_xcvr_native_insts[2].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface
Error(175022): The HSSI_GEN3_X8_PCIE_HIP could not be placed in any location to satisfy its connectivity requirements
Error(175022): The HSSI_RX_PLD_PCS_INTERFACE could not be placed in any location to satisfy its connectivity requirements
Info(175029): 1 location affected
Info(175029): HSSIGEN3X8PCIEHIP_L0
*.rpt files are not generated.
What should I do now?
