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mwac__'s avatar
mwac__
Icon for New Contributor rankNew Contributor
11 months ago

Error: (vsim-3033), Error Loading Design

I'm trying to generate a clock of 20 MHz from altera IP core. I've instantiated the IP Core in my top level design and wrote a test bench. When I try to simulate the design the error can be seen in the transcript window.

The error is of vsim3303. Instantiation of 'altera_pll' failed. The design unit was not found.

Concerned files are attached for convenience. Do let me know if any other information is required.

Thank You.

Pcie

4 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    11 months ago

    All the simulation now run in the msim.tcl as they include all the necessary lib to be compile, for the full steps, you can follow: 1.1. Prerequisites , remember to click on the bottom for the next steps.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    11 months ago

    As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.