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mwac__
New Contributor
New ContributorError: (vsim-3033), Error Loading Design
I'm trying to generate a clock of 20 MHz from altera IP core. I've instantiated the IP Core in my top level design and wrote a test bench. When I try to simulate the design the error can be seen in t...
KennyT_altera
Super Contributor
Super ContributorAs we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
