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mwac__
New Contributor
New ContributorError: (vsim-3033), Error Loading Design
I'm trying to generate a clock of 20 MHz from altera IP core. I've instantiated the IP Core in my top level design and wrote a test bench. When I try to simulate the design the error can be seen in t...
KennyT_altera
Super Contributor
Super ContributorAll the simulation now run in the msim.tcl as they include all the necessary lib to be compile, for the full steps, you can follow: 1.1. Prerequisites , remember to click on the bottom for the next steps.
