EMIF writing to DDR through AVMM speed issue

Question

Hello,I am using Arria 10 device based plateform (HAN Pilot - Terasic) and I want to write data to an FPGA side DDR4 with EMIF.I control this EMIF with avalon memory mapped interface (avmm) but I believe that I reached its maximum throughput and this is slowing me down for writing 256b of data at a rate of 250 MHz. When I issue a write command, I have to wait for the "amm_waitrequest" (also called ~amm_ready) signal from the EMIF to be released which takes a while. Here is a signaltap diagram showing the waitrequest and write signals, compared with the above data updating much faster. Since the waitrequest is too long, the amm_writedata[256] is updated at a much slower rate :Since the waitrequest is the issue there, I suppose the whole AVMM interface is the issue. Is there any way to speed up the interface, or should I rather use another interface, like DMA ?Thanks

sstrell · Answer

Are you using Platform Designer?  Are there any other components connected in a system design that could be causing waitrequest to remain high longer than expected?

rled64 · Answer

Yes I am, the EMIF is accessed both from a customized IP (called Capture) that writes data through AVMM, and from the HPS through an AVMM bridge. Normaly the HPS doesn't issue any read during the write operation from Capture but I can check this indeed.
Do you think the high state of waitrequest is abnormally long compared to a nominal behavior ? Here it is 8 times slower than the 250 MHz desired writing frequency.

Here is a capture of the platform designer with the customized ip Capture and the avmm bridge :

sstrell · Answer

This is why you usually want to use dedicated memory for the HPS instead of going through the H2F bridge if possible. Is there a reason why you are going through an additional pipeline bridge for the HPS to access the memory?

As to the length of the waitrequest, you would need to look at what's happening with the pipeline bridge accessing the RAM.

rled64 · Answer

I'm afraid I lack of knowledge there. My goal is that I want to be able to read data incoming from an ADC on a very wide time window, which for instance would be 1 GB of data generated. I cannot use FIFO or onchip RAM because it's not its purpose on sizes this big, so I'm writing these data to a RAM.
So the FPGA side should be able to write this data to RAM in real time, I mean faster than the generated data rate. And the HPS side should be able to read it after this was written, it can be delayed, and at it's own speed it's not a matter.
Is there another solution there instead of using an FPGA side RAM which obligates me to access it through H2F from HPS ?
I would like to write on a dedicated HPS RAM memory but I guess I was just afraid of timing issues. if the FPGA can access it in real time then I should go for it.

rled64 · Answer

Hello sstrell,I tried to observe bridges and emif signals deeper through signaltap, but I couldn't see anything relevant. The mm_bridge_1 I added between the H2F and EMIF is only for accessing with read operations from HPS, but I could see this is never triggered during the write operation from FPGA (from the Capture IP). Only the write operation here from FPGA is slow.I was wondering if this could be caused by timing requirement issues ? I want to send write to EMIF at a rate of 250MHz, but the EMIF pll_refclk is 266 MHz in order to generate the memory clock of 1066 MHz. Might the writing clock and ref clock be too close for a proper functioning ? I have this timing requirements not met after compiling : Can I duplicate EMIF IP in order to proceed with parallel writes but slower writes (like 2 EMIF at 125 MHz) ? I strongly suppose this is not possible but I try to find workarounds. Also the easy solution would be to store temporarily through a FIFO, but this is limited in size (max ~130k word), hence the DDR4 memory which was &gt; 1GB.Do not hesitate if you need more information,Thank you in advance for your insight

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EMIF writing to DDR through AVMM speed issue

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