Occasional Contributor
Super ContributorThis is why you usually want to use dedicated memory for the HPS instead of going through the H2F bridge if possible. Is there a reason why you are going through an additional pipeline bridge for the HPS to access the memory?
As to the length of the waitrequest, you would need to look at what's happening with the pipeline bridge accessing the RAM.
Occasional ContributorI'm afraid I lack of knowledge there. My goal is that I want to be able to read data incoming from an ADC on a very wide time window, which for instance would be 1 GB of data generated. I cannot use FIFO or onchip RAM because it's not its purpose on sizes this big, so I'm writing these data to a RAM.
So the FPGA side should be able to write this data to RAM in real time, I mean faster than the generated data rate. And the HPS side should be able to read it after this was written, it can be delayed, and at it's own speed it's not a matter.
Is there another solution there instead of using an FPGA side RAM which obligates me to access it through H2F from HPS ?
I would like to write on a dedicated HPS RAM memory but I guess I was just afraid of timing issues. if the FPGA can access it in real time then I should go for it.
