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NalexFPGA's avatar
NalexFPGA
Icon for New Contributor rankNew Contributor
3 years ago

EMIF IP throwing error,Stratix 10

A design with DDR4 needs to be tested. For this I used EMIF IP as a controller for the DDR4.But when I tried to synthesise the project I got this error

Error(20181): The permit_cal input port of IOPLL "EMIF_i|emif_s10_0|arch|arch_inst|pll_inst|pll_inst" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "EMIF_i|emif_s10_0|arch|arch_inst|pll_inst|pll_inst" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "pll_i|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll"

I searched for the same parameter in the EMIF configuration window and couldn't find it.

What can be done to fix this error?

5 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi NalexFPGA,


    Thank you for submitting your question in Intel Community.

    I'm Adzim from Global Application Engineer will assist you in this thread.

    I'm sorry for the delay to provide a response to you last week due to my health condition.


    Have you use the Platform Designer to make connection to the EMIF?

    The suggestion from the error given was asking to check on Platform Designer GUI.


    May I know how you create the EMIF IP and produce the error?


    Regards,

    Adzim


    • NalexFPGA's avatar
      NalexFPGA
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thanks for your reply AdzimZM_Intel.

      I added the EMIF IP from the IP catalog. I added the EMIF instance to the top and connected the EMIF's .pll_ref_clk to a clock generated from PLL(IOPLL Intel FPGA IP).

      I couldn't see any pin named permit_cal on the EMIF IP and couldn't find a way to enable it.

      I checked the IP in the platform designer GUI and the permit_cal pin is not available in it also.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi NalexFPGA,


    I believe the pll_ref_clk signal need to be exported.

    Try to resolve the warning inside the Platform Designer first before generate the design.


    You also can create a design example from EMIF IP GUI to test the DDR4 memory interface.


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.