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NalexFPGA's avatar
NalexFPGA
Icon for New Contributor rankNew Contributor
3 years ago

EMIF IP throwing error,Stratix 10

A design with DDR4 needs to be tested. For this I used EMIF IP as a controller for the DDR4.But when I tried to synthesise the project I got this error Error(20181): The permit_cal input port of IO...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi NalexFPGA,


I believe the pll_ref_clk signal need to be exported.

Try to resolve the warning inside the Platform Designer first before generate the design.


You also can create a design example from EMIF IP GUI to test the DDR4 memory interface.


Regards,

Adzim