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NalexFPGA's avatar
NalexFPGA
Icon for New Contributor rankNew Contributor
3 years ago

EMIF IP throwing error,Stratix 10

A design with DDR4 needs to be tested. For this I used EMIF IP as a controller for the DDR4.But when I tried to synthesise the project I got this error Error(20181): The permit_cal input port of IO...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi NalexFPGA,


Thank you for submitting your question in Intel Community.

I'm Adzim from Global Application Engineer will assist you in this thread.

I'm sorry for the delay to provide a response to you last week due to my health condition.


Have you use the Platform Designer to make connection to the EMIF?

The suggestion from the error given was asking to check on Platform Designer GUI.


May I know how you create the EMIF IP and produce the error?


Regards,

Adzim


  • NalexFPGA's avatar
    NalexFPGA
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thanks for your reply AdzimZM_Intel.

    I added the EMIF IP from the IP catalog. I added the EMIF instance to the top and connected the EMIF's .pll_ref_clk to a clock generated from PLL(IOPLL Intel FPGA IP).

    I couldn't see any pin named permit_cal on the EMIF IP and couldn't find a way to enable it.

    I checked the IP in the platform designer GUI and the permit_cal pin is not available in it also.