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Altera_Forum's avatar
Altera_Forum
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14 years ago

Dsp builder simulation differs from implementation

Hi, i had a macro that enhance contras of images done with System generator of Xilinx. It works great and i made a copy for Altera targets using DSP Builder.

I validated my project running simulation in both Xilinx ,Altera macros in Matlab Simulink comparing the results and i got the same.

Then i have incapsulated the Altera macro in a SOPC component interfaced by an altera Avalon Streaming to the rest of the design.

After some difficulties, now i can use the macro but the results are very very poor.

Do you have any advice?

The macro have 2 clock domains, i used a pll and the Tsamp block to cross clock domain.

The macro contains fifo comparator and other stuff.

I repeat i got perfect simulation

Thank you

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i'm not sure but i think i've found the problem.

    Is the Altbus component, or its implementation.

    I take a 10 bit signed and i want an 8 bit unsigned, so i use the Alt bus to do the cast.

    When the data input is -32, in simulation i get correctly 0 in output, but in implementation i get FF.

    Beside this, i've also noticed that adding signal tab to these signals, make this piece of design correctly work, maybe it adds some constraints...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Looks like it's incorrectly saturating as if the number was signed.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Actually it's not that. It re-interprets it as unsigned and then treats it as a very large unsigned number. Anyway it's clearly wrong.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thanks for your reply, i think i will use a comparator....

    another problem that i have is how to correctly take data in output of my macro.

    Data flow internally at 2x speed and before output i downsample it.

    Xilinx have a downsample block that takes 1 sample every two, specifically the 2nd sample . For example if i have these samples:

    1 2 3 4 5 6

    it takes

    2 4 6

    I do the same in Altera by placing a register before the Tsamp block.

    I get the same simulation results that I get from the Xilinx model. But when i look data in signal tap, data is not right, maybe the clock outside the macro (the SOPC Builder system clock) is not in phase with the internally generated clock, but it's strange because the internal clock is generated by the same PLL as the SOPC Builder system clock.

    Frequency is not that high 65MHz (inside the macro is 130 MHz). I use a Cyclone III with few resources left.