Dsp builder simulation differs from implementation

thanks for your reply, i think i will use a comparator....

another problem that i have is how to correctly take data in output of my macro.

Data flow internally at 2x speed and before output i downsample it.

Xilinx have a downsample block that takes 1 sample every two, specifically the 2nd sample . For example if i have these samples:

1 2 3 4 5 6

it takes

2 4 6

I do the same in Altera by placing a register before the Tsamp block.

I get the same simulation results that I get from the Xilinx model. But when i look data in signal tap, data is not right, maybe the clock outside the macro (the SOPC Builder system clock) is not in phase with the internally generated clock, but it's strange because the internal clock is generated by the same PLL as the SOPC Builder system clock.

Frequency is not that high 65MHz (inside the macro is 130 MHz). I use a Cyclone III with few resources left.