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Altera_Forum
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14 years ago

Dsp builder simulation differs from implementation

Hi, i had a macro that enhance contras of images done with System generator of Xilinx. It works great and i made a copy for Altera targets using DSP Builder. I validated my project running simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

i'm not sure but i think i've found the problem.

Is the Altbus component, or its implementation.

I take a 10 bit signed and i want an 8 bit unsigned, so i use the Alt bus to do the cast.

When the data input is -32, in simulation i get correctly 0 in output, but in implementation i get FF.

Beside this, i've also noticed that adding signal tab to these signals, make this piece of design correctly work, maybe it adds some constraints...