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Jessica's avatar
Jessica
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6 years ago

Differences in the use of Random Number Generator IP Core between Straitx IV and Arria 10

Simulate the Random Number Generator IP Core with ModelSim. The same testbench, when choosing different devices, the simulation results of rand_num_data are quite different.

(1) When stratix iv (EP4SGX230KF40I3) is selected, rand_num_data is not synchronized with inclk. And when the clock frequency is increased to 320MHz, rand_num_data will have an indeterminate state Z.

(2) When Arria 10 (10AX027H4F34I3SG) is selected, rand_num_data is synchronized with inclk. And when the clock frequency is increased to 320MHz, rand_num_data is still output normally. So I would like to ask, when using the Random Number Generator IP Core, what are the different considerations for different devices?

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  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Sorry for the delay. I have been out of office for the past week. Regarding your latest compilation error, it seems like the default built in library which suppose to be to available in the Modelsim Intel FPGA Edition could not be found during the compilation ie altera_mf.

    I am not sure why your compilation is unable to locate these libraries but as a workaround, you can force compile all these libraries to your local folder. You can do the following in msim_setup.tcl:

    1. Change "QUARTUS_INSTALL_DIR" to your local Quartus installation folder at line 114

    2. Comment out "if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {" at line 145 and its corresponding "}" at line 178

    3. Commenout "if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {" at line 186 and its corresponding "}" at line 215

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Just would like to follow if the previous note on editing the msim_setup.tcl to compile libraries helps?

    Thank you.

    • Jessica's avatar
      Jessica
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      6 years ago

      Hi,

      I have been changed the msim_setup.tcl. But, when I type "ld", there will appear many errors which are the same as before.

      Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Thanks for sharing the msim_setup.tcl. I notice that you have commented all the libraries compilation related lines in the msim_setup.tcl. Sorry for any confiusion, please try to comment out only the following lines as in one of my previous notes:

    1. Change "QUARTUS_INSTALL_DIR" to your local Quartus installation folder at line 114

    2. Comment out "if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {" at line 145 and its corresponding "}" at line 178

    3. Commen out "if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {" at line 186 and its corresponding "}" at line 215

    Only 5 lines 114, 145, 178, 186 and 215 are to be commented out.

    Please let me know if there is any concern. Thank you.

    • Jessica's avatar
      Jessica
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      6 years ago

      Hi,

      Thanks for your reply. The simulation has been successfully implemented. But I noticed that the clock is 100MHz. I tried to increase the clock to 3200ps, there will be some other wrong with the results of simulation.

      Thank you.

    • Jessica's avatar
      Jessica
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      6 years ago

      Hi,

      ​

      I want to simulate the quartus project containing random IP core. I followed the steps of "processing-start-start testbench template writer" but couldn't generate the testbench.

      ​

      Then I saw a paragraph in msim_setup.tcl, as shown in the figure. But I'm not sure how to use "ip-setup-simulation --quartus-project = <quartus project>". When I type it in the tcl console in quartus, there will appear errors. When I input it in modelsim-altera, there also many errors.

      ​

      Looking forward to your reply, thank you!

    • Jessica's avatar
      Jessica
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi,

      Continuing the previous reply, I added a figure about the errors of tcl console.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Regarding your observation where when increasing the frequency of the clock for SIV rand generator IP simulation, the simulation seems to have issue. For your information, I am able to replicate similar observation when increasing the frequency from 100MHz to 200MHz. I believe this is due to limitation of the simulation model at high frequency. However, in actual hardware implementation, the core performance should be limited your timing closure. As a workaround, you can simulate the functionality at 100MHz and then implement the actual frequency in your design.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • Jessica's avatar
      Jessica
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi,

      I will implement in my actual hardware.

      Thanks very much!

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Regarding the test bench template writer, for your information, I do not have much insight into it. Generally I would code the test bench from scratch or use the example design generated by the IP. However, for the SIV rand IP, seems like there is no example design generation supported. Sorry for the inconvenience. As a workaround, I would like to recommend you to code your test bench in RTL.

    Please let me know if there is any concern. Thank you.

    Best regards,

    Chee Pin

    • Jessica's avatar
      Jessica
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hi,

      I will do as you recommended.

      Thank you!

    • Jessica's avatar
      Jessica
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi,

      ​

      I ran into a difficult problem. When using the 17.1 standard version to create a random number IP, an error will be reported, see the text and the attachments.

      I am very anxious and look forward to your reply, thank you.

      ​

      ​

      Error: rand_gen_0: IP geneneration failed at file discovery, please tell Altera

      Error: couldn't open "C:/Users/ADMINI~1/AppData/Local/Temp/alt8408_4688452438430321239.dir/0002_rand_gen_0_gen//rand_gen.prj/components/altera_rand_gen/altera_rand_gen_internal_hw.tcl": no such file or directory

      while executing

      "discover_files $proxy_file_set $tmp_dir"

      (procedure "generate_all" line 16)

      invoked from within

      "generate_all $output_name QUARTUS_SYNTH"

      (procedure "generate_quartus_synth" line 2)

      invoked from within

      "generate_quartus_synth rand_num_gen_rand_gen_0"

      Error: qsys-generate failed with exit code 1: 2 Errors, 0 Warnings

      ​

      • CheepinC_altera's avatar
        CheepinC_altera
        Icon for Regular Contributor rankRegular Contributor
        5 years ago
        Hi, As I tested on my side generating the IP with similar configuration as yours in SIV and A10 in Q17.1Std, seems like I have no issue generating the files. Probably you can further look into if there is any permission issue on the generation location? Or you can also try with other Quartus or workstation to see if similar issue still persist. Thank you. Best regards, Chee Pin