Differences in the use of Random Number Generator IP Core between Straitx IV and Arria 10

Hi,

Regarding your observation where when increasing the frequency of the clock for SIV rand generator IP simulation, the simulation seems to have issue. For your information, I am able to replicate similar observation when increasing the frequency from 100MHz to 200MHz. I believe this is due to limitation of the simulation model at high frequency. However, in actual hardware implementation, the core performance should be limited your timing closure. As a workaround, you can simulate the functionality at 100MHz and then implement the actual frequency in your design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin