Differences in the use of Random Number Generator IP Core between Straitx IV and Arria 10

Hi,

I will add some explanations. Quartus Prime Standard 17.0 is used. And the following picture shows the device families the IP core supported. Including Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix 10, Arria 10, Arria II GX, Stratix V and Stratix IV.

​The RTL Viewer of my project:

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1、stratix iv simulation record:

① inclk is 3.124 ns: ② inclk is 100 ns:

③ inclk is 1000 ns:

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2、arria ii simulation record: inclk is 3.124 ns,

① ​arria_ii_GZ:

② ​arria_ii_GX:

There was no improvement in frequency reduction and replacement speed grade.

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3、stratix v、arria 10、cyclone v simulation record: inclk is 3.124 ns,

① stratix v:

② arria 10:

③​ cyclone v:

​So, I want to determine if stratix iv can use the random number generator IP core. If I can use it, do I need some specific settings? Or is these different results caused by the quartus version?

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Hi,

As I understand it, you observe some issue with the SIV random number generator IP in Modelsim simulation where at 320MHz, there seems to be Z at the output. To facilitate further debugging, would you mind to share with me a simple test design and test bench which could replicate the observation? Please share with me the specific Quartus version that you are using as well.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Thanks for your update and sharing of the files. When you are referring to "qsim", just would like to check with you if you are referring to another simulator other than Modelsim? If yes, this may be help to further narrow down the issue.

Just would like to check with you if you have had a chance to try at SIV hardware to see if similar issue occur? This could help to isolate from simulation and also could act as a workaround for you to proceed with SIV design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Just would like to follow up with you on my previous inquiries. Please let me know if there is any concern. Thank you.

Hi,

Just to update you on the latest debugging finding from my side. For your information, I have created a simple simulation design in SIV and A10 in Q17.0Std for issue replication.

The following are my observations:

1. In SIV simulation, I observe that the rand_num_data is rising-edge aligned with clock. The similar observation applies to A10 simulation as well where the output dat ais rising-edge aligned with clock.

2. For your information, as I further look into your SIV simulation screenshot and compare with your A10 simulation and my SIV/A10 simulations, I observe that your rand_num_ready backpressure input signal in SIV simulation seems to be toggling together with the inclk. In your A10 simulation and my simulations, the rand_num_ready seems to be always high. I believe due to the backpressure signal, somehow it cause your simulation to be not rising edge aligned. Would you mind to edit your test bench to tied rand_num_ready to high to see if it helps?

3. I also observe in my simulations when the clock frequency is getting higher ie >300MHz, the output will become invalid. When I lower down the frequency, then the output is back to normal. I believe this is due to the limitation of the simulation model. As a workaround, you can perform functional simulation at lower frequency then increase the frequency to your target frequency in hardware.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Thanks for your update. For your information, I have sent you a simple SIV simulation design through email which I am using to test the SIV random number generator simulation in Q17.0Std. You may do the following to run the with Modelsim Intel FPGA Edition 10.5b:

1. Unzip the file

2. Open Modelsim and change directory to siv_randnum\siv_rand\simulation\mentor

3. Type "source msim_setup.tcl"

4. Type "ld" to compile

5. Type "do wave.do" to populate the waveform

5. Type "run -all" to start simulation

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Regarding your inquiry on "University Program VWF", sorry as I am not really familiar with this and could not comment further. Sorry for the inconvenience. Generally I will generate the IP and simulation model from Megawizard, create test bench and then run simulation in Modelsim.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Thanks for your update. AS I understand it, you observe some issue when trying to run the simulation with the example that I shared to you. For your information, I have re-downloaded the zip sent to you and rerun the steps using Modelsim - Intel FPGA Edition 10.5b and the simulation seems to be working fine.

As I look into the error message that you have encountered, it seems to prompt about unable to compile "altera_mf_components.vhd". Based on my understanding from the msim_setup.tcl, if you are using Modelsim Intel FPGA Edition, it has built in library for this and the "ld" commands would not attempt to compile this library.

Just would like to check with you which specific Modelsim version that you are using to compile? If it is not Modelsim Intel FPGA Edition, you might need to edit the msim_setup.tcl to set the "QUARTUS_INSTALL_DIR" parameter correctly before you open and compile the files in Modelsim.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Just would like to follow up with you on this. Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

Hi,

Just would like to follow up with you on this. Please let me know if there is any concern. Thank you.