New Contributor
Regular ContributorHi,
Just to update you on the latest debugging finding from my side. For your information, I have created a simple simulation design in SIV and A10 in Q17.0Std for issue replication.
The following are my observations:
1. In SIV simulation, I observe that the rand_num_data is rising-edge aligned with clock. The similar observation applies to A10 simulation as well where the output dat ais rising-edge aligned with clock.
2. For your information, as I further look into your SIV simulation screenshot and compare with your A10 simulation and my SIV/A10 simulations, I observe that your rand_num_ready backpressure input signal in SIV simulation seems to be toggling together with the inclk. In your A10 simulation and my simulations, the rand_num_ready seems to be always high. I believe due to the backpressure signal, somehow it cause your simulation to be not rising edge aligned. Would you mind to edit your test bench to tied rand_num_ready to high to see if it helps?
3. I also observe in my simulations when the clock frequency is getting higher ie >300MHz, the output will become invalid. When I lower down the frequency, then the output is back to normal. I believe this is due to the limitation of the simulation model. As a workaround, you can perform functional simulation at lower frequency then increase the frequency to your target frequency in hardware.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi,
I have uploaded more detailed simulation record in the first answer for this question. In the record, I set the rand_num_ready to be always high. But it has no effect.
And about the "qsim", it refers to "University Program VWF" in Quartus Prime software.
This picture shows the simulation results of ".vwf" file (when using Stratix IV in 500MHz).
And I want to know the reason for the differences of ".vwf" file and Modelsim simulation.
Thank you.
