Debugging PCIe DMA transfer example design

Hi @Sijith,

You mean I have to add th clock signal that drives the source_data and fifo_o_out_readdatain the SignalTap GUI window to view it? Then The signalTap should run in some different clock? I mean the default clock? (currently signal tap is running in the same clock as clock signal that drives the source_data and fifo_o_out_readdata .

>> Yes, please add the clock signal that drives the source_data and fifo_o_out_readdata in the SignalTap so that we can view the clock signal in the SignalTap GUI window. Also, add the signals that carry the data before the data is passed to the fifo_o_out_readdata signal from source_data to check if the correct data is passed from the source to FIFO.

But in this case I gets error when I add signal tap instance and at nodes that where the design connects to DDR4 pins (I believe I did it correctly), the error "Error(17046): Illegal connection found on I/O output buffer primitive u0|emif_ddr4_b|emif_ddr4_b|arch|arch_inst|bufs_inst|gen_mem_a.inst[1].b|cal_oct.obuf to DDR4B_A[1]. The IO output buffer should only drive out to a top-level pin" happens when try to signal Tap at the node `DDR4B_A[1]`. I dont know why it is illegal to do so in this case?

(Screenshot of selected nodes are attached) FYI: My intention was to see the data flow (that created in the data generator and then streaming through avlonFIFO) to the DDR4

>> Can you please attach the original PCIe DMA transfer example design (without any modification) that you mentioned and include the steps to replicate the error for me to replicate the error at my end to further investigate the issue? Please let me know if you want to send the design via email.

Thanks.

Best Regards,

VenTingT