Debugging DisplayPort IP

Question

HiWe have used quartus 19.3 to generated example design for a DisplayPort targeting Cyclone 10 GX Development Kit + Bitec DP Daughter card. There were instructions for generating Tx-Only design from the example design and we were able to generate Tx-only design that worked fine for color bars.We have re-targeted this design on to a custom board containing CY10GX FPGA. Link training on AUX channel is happening properly and the command log matches with that of a working design. MSA attributes also display correct values. But for some reason, DP_TX goes into Video Idle Pattern DPTX_TX_CONTROL[3:0]. Because of this monitor goes into Sleep mode. Are there any recommended steps for debugging the DP design on a custom board?How do we root cause the issue that is driving DP_TX into Video Idle mode ? The problem could also be on our custom board.Regards

deshi_intel · Answer

HI,Perhaps you can evaluate your video source design first that interact with DP TX designAlso the good news is you already have a working reference design with color bar pattern generator to serve a debug reference When you mentioned you ported over the design to custom board, what's the design changes to be specific ? You want to look into the detail of design changes to help you isolate issue.For instance, is there any changes in Quartus design ? Have you tested the exact working design before with just limited FPGA pinout change to match custom board ?Like wise, what's the board design changes on the custom board as compared to Bitec daughter card ?Thanks.Regards,dlim

bmarp1 · Answer

Thanks for your support.

The video source is clean, its output keeps toggling regularly on SignalTap.

Our custom board has a TI re-driver and a mDP port. TI's re-driver registers look clean and they reflect the link training parameters. But it does not have any registers for main link status.

btc_dptx_is_link_up API was used for identifying the link status. When the link is up, DP_TX goes into NORMAL_VIDEO mode and switches to VIDEO_IDLE mode on link down. But the duration of link up status is so small that nothing is visible on the monitor. Are there any APIs that provide more details into why the link was breaking regularly.

Regards

Bhargav

deshi_intel · Answer

Hi Bhargav,Back to my question earlier, have you used back the working DP design from C10 GX dev kit on your custom board ?If yes and DP link training still failed, then perhaps we are dealing with transceiver link tuning issue on your custom boardFor RX link tuning - Have you sweep different RX equalizer setting in your TI redriver to see if it helps to improve the DP link training result ?For TX link tuning - you can refer to below guideline to learn more about FPGA link tuninghttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an871.pdfSorry we don't have special debug API. Typically we used DP debug test tool equipment to analyze and decode the AUX transaction traffic to debug the difference between good case and bad caseFor instance, I am using UNIGRAF DP test tool for debughttps://www.unigraf.fi/products/displayport-test-toolsThanks.Regards,dlim

bmarp1 · Answer

Thanks for the suggestions.I have ported the working design to the custom board. It's a 4-lane Tx-only Design. I had to edit the clock pll settings and pin/timing constraints to match the custom board. We intend to use only TX XCVRs for DP and RX XCVRs are used for another functionality. The RX has additional components on its path as per that protocol requirements. I will try performing link training with internal loopback and see how it goes.RegardsBhargav

deshi_intel · Answer

Alright, hopefully everything goes well on your side !

Forum Discussion

Debugging DisplayPort IP

6 Replies

Recent Discussions

Agilex 7 R-Tile PIPE Direct Mode: Raw Rx Data Misalignment - Is Soft Word Alignment Needed?

Agilex 7 slew rate reconfiguration

agilex 7 Platform Designer PIO addr width

Regarding MIPI CSI 2 TX

agilex 7 Platform Designer PIO 2x8