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BMarp1's avatar
BMarp1
Icon for New Contributor rankNew Contributor
6 years ago

Debugging DisplayPort IP

Hi We have used quartus 19.3 to generated example design for a DisplayPort targeting Cyclone 10 GX Development Kit + Bitec DP Daughter card. There were instructions for generating Tx-Only design fro...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Perhaps you can evaluate your video source design first that interact with DP TX design

Also the good news is you already have a working reference design with color bar pattern generator to serve a debug reference

When you mentioned you ported over the design to custom board, what's the design changes to be specific ? You want to look into the detail of design changes to help you isolate issue.

  • For instance, is there any changes in Quartus design ? Have you tested the exact working design before with just limited FPGA pinout change to match custom board ?
  • Like wise, what's the board design changes on the custom board as compared to Bitec daughter card ?

Thanks.

Regards,

dlim

  • BMarp1's avatar
    BMarp1
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks for your support.

    The video source is clean, its output keeps toggling regularly on SignalTap.

    Our custom board has a TI re-driver and a mDP port. TI's re-driver registers look clean and they reflect the link training parameters. But it does not have any registers for main link status.

    btc_dptx_is_link_up API was used for identifying the link status. When the link is up, DP_TX goes into NORMAL_VIDEO mode and switches to VIDEO_IDLE mode on link down. But the duration of link up status is so small that nothing is visible on the monitor. Are there any APIs that provide more details into why the link was breaking regularly.

    Regards

    Bhargav