Hi Bhargav,
Back to my question earlier, have you used back the working DP design from C10 GX dev kit on your custom board ?
- If yes and DP link training still failed, then perhaps we are dealing with transceiver link tuning issue on your custom board
- For RX link tuning - Have you sweep different RX equalizer setting in your TI redriver to see if it helps to improve the DP link training result ?
- For TX link tuning - you can refer to below guideline to learn more about FPGA link tuning
Sorry we don't have special debug API.
- Typically we used DP debug test tool equipment to analyze and decode the AUX transaction traffic to debug the difference between good case and bad case
- For instance, I am using UNIGRAF DP test tool for debug
Thanks.
Regards,
dlim
New Contributor
