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Altera_Forum
Honored Contributor
Honored Contributorddr2 sdram
Hello, I'am new to SOPC build,and sorry for my poor english.
I have bought a dsp development kits from alter,and there is an ddr2 sdram on this development board. this is the development kits I have bought: http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1699-nd In my sopc build, i only add there components: niso ii cpu,jtag uart and ddr2 sdram controller megacore funtion - altera corporation I don't know how to fill these parameters about this ddr2 sdram controller,when i generate this cpu by default setting,I found there are some files about pll(such as ddr_pll_cyclonii) are generate by system,I don't konw how to use these files. can anyone help me,or send me a example about,thank you [email protected]17 Replies
Altera_ForumI think it's the way you locate the DDR2 controller on-chip and that is often used to meet some critical path requirements. Keep it as the default.
- Altera_Forum--- Quote Start --- I think it's the way you locate the DDR2 controller on-chip and that is often used to meet some critical path requirements. Keep it as the default. --- Quote End --- May I have your email? Thank you! In my project, I set "memory data width" to 64,and let all others the same as the "standard" project,and assign my pins following the original ddr2 core location But I get this error information when I run "Hello world!" Verifying 10010000 ( 0%) Verify failed between address 0x10010000 and 0x1001001F Leaving target processor paused Thank you
- Altera_Forum
something goes wrong when using the full data width for the DDR2
[email protected] - Altera_Forum--- Quote Start --- something goes wrong when using the full data width for the DDR2 [email protected] --- Quote End --- Do you raise your ddr2 sdram's memory by change "memory data bus width" or change the "chip select"? I found that when I set "memory data bus width" to 32,and let "chip select" to be 1, I can use 128M of the ddr2 sdram.But when I set "chip select" to be 2 or change "memory data bus width" to 64,they both don't work well. I found another phenomenon, quartus9 will assign "dq,dqs,dm" automatically,and you must use these automatically assigned pins,otherwise you will get a "DDIO" error when compile these project.
- Altera_Forum
First of all you can not use 2 chip select cause the DDR2 you are using doesn't support two chip select.
Second, the automatic assignment you are talking about are pre-assigned since you are using the "standard" template. Finally, I am having the same problem when I am trying to increase the data width to 64-bit, it's something I cannot figure out! - Altera_Forum--- Quote Start --- First of all you can not use 2 chip select cause the DDR2 you are using doesn't support two chip select. Second, the automatic assignment you are talking about are pre-assigned since you are using the "standard" template. Finally, I am having the same problem when I am trying to increase the data width to 64-bit, it's something I cannot figure out! --- Quote End --- Thank you! I build a new project, it only contain cput, jtag uart and ddr2 sdram, I am not using the "standard" template.but the quartus still automatic assigg the pins. If quartus didn't assign the pins automatically,and I finish the pins assigment manually, I will get an warning in "Filtter" process,the waring is something about "capacitance",and I can compile this project succefully,but I can't run "hello world" on it.
- Altera_Forum
anybody knows how to sotore data in SDRAM using DSP builder?
thanks!!
