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Altera_Forum's avatar
Altera_Forum
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18 years ago

DDR2 on Stratix II GX PCI-E Dev kit malfuncitoning

hi,

I have Stratix II GX PCI-E Dev kit. I have already successfully ported NIOSII, On-chip RAM, JTAG UART, PIO LED, PLL, MY own LED on it and it works. I had so much trouble with DDR2. I chose high performance DDR2 since I don't need to worry about PLLs, DLLs, feedback PLL. and I was able to add the core to my base working system in SOPC after weeks struggle with regular DDR2.

so, I got all the pin assigned and setup constraints, and compiled my project. of course, whole bunch of warning. My system can run at 100 MHz. and my DDR2 controller internally run at 200Mhz.

Downloaded to the FPGA. LED blinked, JTAG UART works. DDR2 readback test always read me back garbage data.

I used the debugger in NIOs IDE. I can view the DDR2 memory. all garbage data. I was able to read and write to any location in the onchip ram. Simulated the entire system in ModelSIM. the DDR2 core was doing something. I saw clk pair, my data, address and some handshaking signals being generated. I am not sure about the correctness. I guess I don't need to worry since it is from Altera magecore. or Should I?

any idea?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    hi, my pin assignment is completely wrong. I used the pin assignment function in Quartus II and export the assignment as tcl script. Altera support wants me to double check the assignment and I found out the dq are completely wrong. I don't know how that happened. I manually edited my tcl script and my DDR2 works now.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I am sorry to trouble you. I want to ask you a question.

    Does it use external parallel resistors on DQ and DQS pins between stratixII Gx and DDR2 chips on Stratix II GX PCI-E Dev board.

    Now I am designing a stratix III pcb board with two DDR2 chips.

    The space of the pcb board is limited. It can't place so many termination resistors.

    I wonder whether the external parallel resistors is necessary.

    I don't have the schematics of Stratix II GX PCI-E Dev board.

    I look forward to your answer.

    Thanks.

    My Email liuxue0512@tom.com
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello,

    I think you are profession in my issues, I need your help.

    I have some troubles with my design with Stratix II Devices. I use MegaWizard, Quartus's Web edition, to create ALTMEMPHY. It releases many files such as:

    *_alt_mem_phy_reconfig_sii

    *_alt_mem_phy_ sii

    alt_mem_phy_defines

    alt_mem_phy_sequencer.vhd

    *_altmem_phy_sequencer_wrapper.vo

    ...

    Module "alt_mem_phy_sequencer.vhd" is encrypted, so I can't see anything. How can I use this module?

    To ensure my logic is ok, I simulate them with my logic by using NCverilog 5.5. But the way ALTMEMPHY tool uses parameter is new to me. And when I run my simulation, it can not stop and print out may warnings. So you can give me your advice.

    I'm very impressed by ALTMEMPHY but I can't use it for a long time.

    Thank you in advance!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Did you have any luck on porting? I have the same board, but I do not have any simple SOPC example to start on. Could you please share what you did?