DDR2 Controller Config "local_size"

Question

Hello, I am writing a verilog local interface that will read a block of data (131,072 64-bit word) from a fifo and use a DDR2 MegaCore function to store the data in DDR2 memory. I am looking over page 3-26 of the DDR and DDR2 SDRAM Controller Compiler Guide and have a question about the DDR2 input "local_size". I was wondering if anyone could recommend a value?

The documentation says for DDR2 the size could be 2,4,6, or 8. If I understand the manual, and set the size to 8, then I should pulse the local_write_req 16,384 times, or should I keep local_write_req high for 16,384 clock periods? I guess it only makes sense to keep it high rather then pulse the signal. I never used DDR2 before so please excuse my questions.

My application is a PCIe board that I hope to use 8 lanes which would have the PCIe core running a clock frequency of 250Mhz, the data would arrive at that rate into a fifo and my verilog file would read out the data and send it to the DDR2 MegaCore Controller. Does this sound doable? I have never operated at this high of frequency.

Thanks,

joe

altera_forum · Answer

The High Perf DDR2 controller is meant to be attached to an Avalon bus system (created in SOPC Builder). It is of course possible to use it as a standalone module, but you will have to follow the Avalon Bus protocol in order to be able to read/write to it.

If you read the Avalon Bus specification document, you will understand the operation/purpose for each of the DDR2 controller pins.

For example in your case, I assume the local_size input is the Avalon burst size (the number of words you will get back for each read request), which is sort of close to what you said in your post, but simply "pulsing" the read request or keeping it high won't work.

The DDR controller has latency (data valid output), wait request output and also fixed burst size. You will have to read/understand the memory mapped Avalon Bus spec and then write a state machine which observes all these signals if you want to be able to communicate correctly with the controller.

250MHz is quite high and probably not achievable in the low cost Cyclone/Arria families, but with careful coding should be ok for Stratix (you didn't specify if you have an Arria or a Stratix board).

altera_forum · Answer

I see that you're using a PLDA XpressGX2 board. PCIe 8-lane configuration uses a 250 MHz core clock, so the DDR2 controller would operate in full rate mode with 250 MHz memory clock. As far as I know, PLDA didn't ship any DDR2 example designs (respectively they didn't one year ago), so I wonder if the DDR2 hardware has been operated with 250 MHz clock before, I'm missing particularly the SSTL termination at the GX2 board, but the connections are rather short. I had no need to operate the memory with the GX2 board up to now, buf I would ask PLDA support about the intended IO settings for their unusual SSTL circuit respectively a complete reference design. May be it is available in the meantime.

Regarding interface operation, I would notice, that the DDR2 controller (I'm using HP controller with Arria GX now, but I think there's no basic difference) is able of reading or writing full RAM pages continously, interupted occasionally by refresh cycles. So when you're transfering larger blocks, the throughput can be slightly below nominal memory data rate of 500MHz in your case, when the interface is operated correctly.

altera_forum · Answer

Hello all, thank you for responding to my post. I am using the StratixII GX and not using the SOPC builder. Yes, you are correct the board is from PLDA and I must say the code and documentation they provide is above average and I am pleased. Also, they did not provide a Reference Design with the DDR2 included and they tested the DDR2 up to 200Mhz.

I think it would be best to run using 4-lanes which gives a PCIe core clock of 125Mhz. I noticed that when I run the MegaCore Toolbench wizard for the DDR2 controller and then set the clock to 250Mhz I must then modify some parameters to meet timing constraints. But if the clock is 125Mhz then it says I meet all my timing contraints.

I've attached a schematic of the connection to the DDR2 memories. They have 2 banks, with each bank having 2-memory chips. Each bank is 32-bits. Could I use one DDR2 Controller to interface with the full 64-bits? I want to do 64-bit writes and reads. Currently I am not using the HP DDR Controller.

Thanks for taking the time to read my message,

joe

altera_forum · Answer

Hello, you mentioned something very concerning that I need to ask. I'm not using the Avalon Bus, so do you suggest I use the non-HP Controller? I looked over the documentation and I don't see a Full Rate Native Interface Mode only Half Rate, maybe need to use that mode?

altera_forum · Answer

Clancy,

Hello, you mentioned that if I wanted to use the DDR2 HP Controller standalone I needed to use the Avalon addressing protocol but why is there a radio button selection in the Wizard that asks for Native or Avalon?

If I intend to use Native at Full Rate do I select Native and then following the Avalon Addressing Protocol or do I need to select the Avalon button? I'm a little confused.

Do you think it would be easier just to run Half Rate Native Interface Mode? There is a timing diagram for that mode.

Thanks,

joe

Forum Discussion

DDR2 Controller Config "local_size"

5 Replies

Recent Discussions

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Agilex 7 I Series Development Kit: External hardware access error when programming

Inquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5

F-tile 10GBASE-R firecode FEC IP (Agilex 7)

F-Tile Ethernet Hard IP Design Example - Testbench