DDR2 Controller Config "local_size"

The High Perf DDR2 controller is meant to be attached to an Avalon bus system (created in SOPC Builder). It is of course possible to use it as a standalone module, but you will have to follow the Avalon Bus protocol in order to be able to read/write to it.

If you read the Avalon Bus specification document, you will understand the operation/purpose for each of the DDR2 controller pins.

For example in your case, I assume the local_size input is the Avalon burst size (the number of words you will get back for each read request), which is sort of close to what you said in your post, but simply "pulsing" the read request or keeping it high won't work.

The DDR controller has latency (data valid output), wait request output and also fixed burst size. You will have to read/understand the memory mapped Avalon Bus spec and then write a state machine which observes all these signals if you want to be able to communicate correctly with the controller.

250MHz is quite high and probably not achievable in the low cost Cyclone/Arria families, but with careful coding should be ok for Stratix (you didn't specify if you have an Arria or a Stratix board).