DDR2 Controller Config "local_size"

I see that you're using a PLDA XpressGX2 board. PCIe 8-lane configuration uses a 250 MHz core clock, so the DDR2 controller would operate in full rate mode with 250 MHz memory clock. As far as I know, PLDA didn't ship any DDR2 example designs (respectively they didn't one year ago), so I wonder if the DDR2 hardware has been operated with 250 MHz clock before, I'm missing particularly the SSTL termination at the GX2 board, but the connections are rather short. I had no need to operate the memory with the GX2 board up to now, buf I would ask PLDA support about the intended IO settings for their unusual SSTL circuit respectively a complete reference design. May be it is available in the meantime.

Regarding interface operation, I would notice, that the DDR2 controller (I'm using HP controller with Arria GX now, but I think there's no basic difference) is able of reading or writing full RAM pages continously, interupted occasionally by refresh cycles. So when you're transfering larger blocks, the throughput can be slightly below nominal memory data rate of 500MHz in your case, when the interface is operated correctly.