Agrl
New Contributor
3 years agoDDR timing violation
I am getting the violation for the nodes
-0.493 PCIe_X8_SUB_SYSTEM|emif_1|emif_1|ecc_core|core|ecc|internal_master_wr_data_ready PCIe_X8_SUB_SYSTEM|mm_interconnect_0|agent_pipeline_002|gen_inst[0].core|data1[50] PCIe_X8_SUB_SYSTEM|emif_1|emif_1_core_usr_clk PCIe_X8_SUB_SYSTEM|emif_1|emif_1_core_usr_clk 3.752 -0.200 4.067 Slow 900mV 100C Model
I am using LRDIMM. How to resolve this violation