Forum Discussion
Agrl
New Contributor
New ContributorDDR timing violation
I am getting the violation for the nodes
-0.493 PCIe_X8_SUB_SYSTEM|emif_1|emif_1|ecc_core|core|ecc|internal_master_wr_data_ready PCIe_X8_SUB_SYSTEM|mm_interconnect_0|agent_pipeline_002|gen_inst[0]....
AdzimZM_Altera
Regular Contributor
Regular ContributorHi,
I need additional input from you to debug in this timing issue.
Are you able to share the full timing report here? If you can share a design that can replicate the issue also good.
Are you observing timing violation after adding the PCIE IP into the design?
If using only EMIF example design, do you find any timing issue?
You can run DRC in Timing Analyzer GUI. From there, it will generate a list of rules with recommendation that can help to resolve the timing issue.
Regards,
Adzim
