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Agrl's avatar
Agrl
Icon for New Contributor rankNew Contributor
3 years ago

DDR timing violation

I am getting the violation for the nodes -0.493 PCIe_X8_SUB_SYSTEM|emif_1|emif_1|ecc_core|core|ecc|internal_master_wr_data_ready PCIe_X8_SUB_SYSTEM|mm_interconnect_0|agent_pipeline_002|gen_inst[0]....
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


This timing violation is occurred between the EMIF IP block and other block.

Some timing closure techniques can help to resolve the issue.


Can you add pipeline or register to path that has timing violation?


What is the recommendation from DRC report in the Timing Analyzer?



  • Agrl's avatar
    Agrl
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Sir,

    I Checked the DRC it is coming as FMAX has reached its maximum limit. some time i am getting the issue like when i read the DDR. I am getting zero.