Hello, I am trying to do a simple task: I will form an UDP packet in hardware, then I want to move it to Nios, add IP header and send to ethernet. I will split my problem into two parts: I've created avalon streaming source component, so I am able to move the packet to the Nios memory using SGDMA stream to memory, however I am not sure how can I move the packet to the TSE core? TSE also use SGDMA (st-to-mem and mem-to-st), so I can't connect my component to one of those SGDMA inputs, since it is already in use. What are my options? Add another SGDMA Stream-to-memory core and connect to the same memory that TSE SGDMA use? How can I pick the data from the memory using another SGDMA there? Lets say I already have a packet data in Nios, how can I add IP header to the packet using InterNiche? Maybe there are some examples of packet generation using InterNiche? Also I can't find NicheStack documentation anywhere, maybe someone could point me out? I suppose simple packet sending or receiving tasks can be used without RTOS? I have chosen SGDMA because the data stream can reach 50mbps or more, so the Nios should be really fast to add a header to the whole packet, which is almost 1400 bytes. Thank You.

Use sendto() function. For instance, l = sendto(conn->fd, data, pkgLth, 0,(struct sockaddr *)&cliaddr,nLen); By the by can you tell me how you move the data from hardware to Nios processor? Jacky

Maybe there is documentation for all the stack? I am using my custom hardware->Avalon-ST and Avalon-ST-> hardware component. They're very simple to do, since SOPC builder gives templates, when creating a new component.

That's socket programming. I'm not sure if altera has such a document but you can find them in C socket programming template

Since you started generating the udp packet in hardware, why don't you go all the way and generate the IP and Ethernet headers the same way? Then you can use a multiplexer and send your packet directly to the TSE without going through memory. Did you have a look at the UDP offload example? http://www.alterawiki.com/wiki/nios_ii_udp_offload_example

Hm, I am not sure, but I suppose IP header is a bit harder to add in hardware, because of header checksum. Maybe there are full (IP(UDP(RTP))) implementations in hardware? I am checking UDP offload example now, too bad I am bad at verilog :)

Data send thru ethernet | Altera Community

38 Replies

Altera_Forum
Honored Contributor
14 years ago
Socretes your posts have been very helpful to me. I plan on testing out some more of your work later tonight, however did you ever figure out a way to increase the size of the payload? I would suspect part of the speed problem results from not making the ethernet packet as large as possible.
Altera_Forum
Honored Contributor
14 years ago
The largest packet can be somewhere around 1500bytes. My packet is about 1350bytes, so I suppose this is quite good result.
Altera_Forum
Honored Contributor
14 years ago
Ah, alright I was going off of your payload size that you mentioned in June. I was wondering if you have made any changes to your source code that improved throughput I would love to take a look at it.

Edit: For getting hundreds of mbps, I would imagine that you would need to use RGMII and implement the send with gigabit Ethernet protocol, which should give you a payload of ~9000 bytes.
Altera_Forum
Honored Contributor
14 years ago
Well, as You can see, I don't use Nios to form IP packets anymore. All the layers MAC+IP+protocol are generated in hardware.
Altera_Forum
Honored Contributor
14 years ago
A small update:
I've added fill level port to SC FIFO I use on Avalon-ST bus on the output, so after the transmit stop, that fifo is fully filled. Too bad I can't check internal TSE fifo fill level, but I suppose it is also filled to the max. How is this happening? I feed the packets at 50MHz, 32bit bus, but the valid signal occurs so rare, that the input stream is no more than 3.5mbps. I suppose after FIFO fill-up in TSE it drops the ready signal forever?
Altera_Forum
Honored Contributor
14 years ago
So I am completely stuck... If here are any guys done hardware ethernet packets forming and sending to lan please tell me if You used TSE core through SOPC or it was a fully hardware approach? Somehow TSE fifo gets full and I don't understand how MAC can't handle ~3-4mbps stream.

here is the code. (http://pastebin.com/mpbs2xdm)
If aso_ready check is commented, then the data goes a little bit longer... Where could be the problem?
Altera_Forum
Honored Contributor
14 years ago
Can you run a signaltap probe on your streams, especially on the inputs and outputs of the multiplexer?
You should use backpressure to be sure you don't loose data, and I agree that you should get a better throughput than this. One of the components must get stuck at one point, but I never experienced any problem with the TSE's own fifos.
Altera_Forum
Honored Contributor
14 years ago
I've solved the issue using 8->32 bit conversion using fifo. That allows backpressure and the signal is always valid if the packet sending is started when fifo is full enough. Probably if You don't send the packet in a certain amount of time, the tse fifo gets full.

Forum Discussion

Data send thru ethernet

38 Replies

Recent Discussions

Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC

Agilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wanted

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO