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Altera_Forum
Honored Contributor
Honored ContributorData send thru ethernet
Hello, I am trying to do a simple task: I will form an UDP packet in hardware, then I want to move it to Nios, add IP header and send to ethernet. I will split my problem into two parts: ...
Altera_ForumHonored Contributor
Honored ContributorA small update:
I've added fill level port to SC FIFO I use on Avalon-ST bus on the output, so after the transmit stop, that fifo is fully filled. Too bad I can't check internal TSE fifo fill level, but I suppose it is also filled to the max. How is this happening? I feed the packets at 50MHz, 32bit bus, but the valid signal occurs so rare, that the input stream is no more than 3.5mbps. I suppose after FIFO fill-up in TSE it drops the ready signal forever?
