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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Cyclone V DSP Cost 36x36 signed multiplication

Hello.

I have a simple design issue with the multiplication IP LPM_MULT.

The Altera info page arria v cyclone v dsp block (http://www.altera.com/products/fpga/features/dsp/arria-v-cyclone-v-dsp-block.html) tells me that I can implement one independent 36x36 multiplier in multiple-block mode with an amount of 2 DSP blocks. If I do so in an simple Quartus Project with Quartus Prime Version 17.1.0 Built 590 I get an amount of 3 DSP Blocks, 54 ALUTs and 27 ALMs needed. This is deviant from the used FPGA. For reference: Cyclone V 5CSEBA5U23C7.

All Analysis & Synthesis Settings and also all Fitter Settings are set to default values (it's a new project with this IP and a vhdl file)

The Resource Utilization by Entity report tells me that 3 DSP blocks are used for this multiplication instead of 2. I've tested every option of the IP with no effect to reach the 2 DSP blocks.

Has anyone a hint or idea what is going wrong here?

Thanks in advance.

2 Replies

  • MTw's avatar
    MTw
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello,

    I've asked this question in the old Altera Forum. This is quite a few days in the past. Regardless of that fact I still need an answer.

    The posted link is not longer available so here is the new one:

    https://www.intel.com/content/www/us/en/products/programmable/fpga/arria-v/features.html?language=en_US

    Arria V and Cyclone V FPGA Multipliers in Multiple-Block Mode, One independent 36x36 multiplier with 2 DSP blocks (requires additional logic outside the DSP block)

    Does anyone has a hint or idea?

    Thanks in advance.

  • Daixiwen's avatar
    Daixiwen
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    I can reproduce the problem but unfortunately I don't see a solution. According to the documentation each block should be able to do two independent 18*19 bit multiplications. As you need 4 of them to do a 36*36 multiplication, 2 blocks should be enough.

    Looking at the technology viewer after synthesis, it looks like Quartus does combine the two multiplications that must be summed (high word of one operand by low word of the other) in a single block, but uses two other blocks for the other two multiplications. I tried tweaking a bit with the project settings, to no effect. Using some VHDL code instead of the LPM_MULT block produces the same results. Even forcing the maximum available DSP blocks to 2 doesn't do the trick. There is either a bug in Quartus or a limitation in the usage of those multiply blocks that is not documented. Or am I missing somtething obvious?

    If this is causing problems with available resources for your project you should either contact Intel trough mysupport or call your local FAE