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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Cyclone V DSP Cost 36x36 signed multiplication

Hello. I have a simple design issue with the multiplication IP LPM_MULT. The Altera info page arria v cyclone v dsp block (http://www.altera.com/products/fpga/features/dsp/arria-v-cyclone-v-d...
MTw's avatar
MTw
Icon for New Contributor rankNew Contributor
8 years ago

Hello,

I've asked this question in the old Altera Forum. This is quite a few days in the past. Regardless of that fact I still need an answer.

The posted link is not longer available so here is the new one:

https://www.intel.com/content/www/us/en/products/programmable/fpga/arria-v/features.html?language=en_US

Arria V and Cyclone V FPGA Multipliers in Multiple-Block Mode, One independent 36x36 multiplier with 2 DSP blocks (requires additional logic outside the DSP block)

Does anyone has a hint or idea?

Thanks in advance.