cyclone II ALTLVDS_RX ipcore issue？

i am using ALTLVDS_RX ipcore on cyclone II device, but meet a problem that rx parral datas are not correct. the following is the ipcore configration. any advice?

ALTLVDS_RX_component.buffer_implementation = "RAM",

ALTLVDS_RX_component.cds_mode = "UNUSED",

ALTLVDS_RX_component.common_rx_tx_pll = "OFF",

ALTLVDS_RX_component.data_align_rollover = 4,

ALTLVDS_RX_component.data_rate = "519.75 Mbps",

ALTLVDS_RX_component.deserialization_factor = 7,

ALTLVDS_RX_component.dpa_initial_phase_value = 0,

ALTLVDS_RX_component.dpll_lock_count = 0,

ALTLVDS_RX_component.dpll_lock_window = 0,

ALTLVDS_RX_component.enable_clock_pin_mode = "UNUSED",

ALTLVDS_RX_component.enable_dpa_align_to_rising_edge_only = "OFF",

ALTLVDS_RX_component.enable_dpa_calibration = "ON",

ALTLVDS_RX_component.enable_dpa_fifo = "UNUSED",

ALTLVDS_RX_component.enable_dpa_initial_phase_selection = "OFF",

ALTLVDS_RX_component.enable_dpa_mode = "OFF",

ALTLVDS_RX_component.enable_dpa_pll_calibration = "OFF",

ALTLVDS_RX_component.enable_soft_cdr_mode = "OFF",

ALTLVDS_RX_component.implement_in_les = "ON",

ALTLVDS_RX_component.inclock_boost = 0,

ALTLVDS_RX_component.inclock_data_alignment = "EDGE_ALIGNED",

ALTLVDS_RX_component.inclock_period = 13468,

ALTLVDS_RX_component.inclock_phase_shift = 1684,

ALTLVDS_RX_component.input_data_rate = 519,

ALTLVDS_RX_component.intended_device_family = "Cyclone II",

ALTLVDS_RX_component.lose_lock_on_one_change = "UNUSED",

ALTLVDS_RX_component.lpm_hint = "CBX_MODULE_PREFIX=lvds_rx",

ALTLVDS_RX_component.lpm_type = "altlvds_rx",

ALTLVDS_RX_component.number_of_channels = 8,

ALTLVDS_RX_component.outclock_resource = "AUTO",

ALTLVDS_RX_component.pll_operation_mode = "SOURCE_SYNCHRONOUS",

ALTLVDS_RX_component.pll_self_reset_on_loss_lock = "UNUSED",

ALTLVDS_RX_component.port_rx_channel_data_align = "PORT_UNUSED",

ALTLVDS_RX_component.port_rx_data_align = "PORT_UNUSED",

ALTLVDS_RX_component.refclk_frequency = "UNUSED",

ALTLVDS_RX_component.registered_data_align_input = "UNUSED",

ALTLVDS_RX_component.registered_output = "ON",

ALTLVDS_RX_component.reset_fifo_at_first_lock = "UNUSED",

ALTLVDS_RX_component.rx_align_data_reg = "UNUSED",

ALTLVDS_RX_component.sim_dpa_is_negative_ppm_drift = "OFF",

ALTLVDS_RX_component.sim_dpa_net_ppm_variation = 0,

ALTLVDS_RX_component.sim_dpa_output_clock_phase_shift = 0,

ALTLVDS_RX_component.use_coreclock_input = "OFF",

ALTLVDS_RX_component.use_dpll_rawperror = "OFF",

ALTLVDS_RX_component.use_external_pll = "OFF",

ALTLVDS_RX_component.use_no_phase_shift = "OFF",

ALTLVDS_RX_component.x_on_bitslip = "ON",

ALTLVDS_RX_component.clk_src_is_pll = "off";