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manu-solystic's avatar
manu-solystic
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3 years ago
Solved

Cyclone 10GX PCI express without clk_user any solution ?

I have a prototype design with a Cyclone 10GX

I want to use the PCI express , but the clk_user is not connected
And if i read the documentation about the PCI express with cyclone 10Gx , this clock seems to be mandatory

But on my design, it's not possible to connect the CLK_USR (The pin is not accessible)

Does any have a suggested solution, to have a a PCI express working
With the use of a other clock connected to the FPGA. with an internal connection.
I have a 100Mhz LVDS clock connected to the Cyclone 10GX, and I have also a 25Mhz HCMOS clock connected to the FPGA

These clock are used in the Cyclone 10GX design

Thanks for any answer

Regards

Manuel Ribeiro

  • manu-solystic's avatar
    manu-solystic
    3 years ago

    Hi,

    So I understand that the only solution is to connect a clock on the clkuser pin

    So you can close this ticket

    regards

13 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Can I know which document you are referring to ?

    Can you share it with me to ensure that we both in the same channel.


    Regards,

    Wincent_Intel


  • manu-solystic's avatar
    manu-solystic
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi

    Thanks for your answer
    So I am using a cyclone 10GX FPGA 10CX085YF672E6G on my design

    And i want to test the PCI express on my design
    I use the folowing Intel Example

    1) - Cyclone 10 GX - PCIe Gen1 x1 Avl-ST

    2) - Cyclone 10 GX - CvP Initialization Design Example

    Theses design does not work on my board,

    Clk_usr (pin AC13) is not connected on my design, and i cannot connect any signals on this pin,

    Because this pin is not accessible (no via, or pin_escape to access for this pin)

    So I want to know

    Do i need the clk_usr for the pci express HIP,
    Can I use another clock already connected on my degin

    On my design I have a 25Mhz clock, and a 100Mhz Clock,

    I ask if there is any way to use pci express without clk_usr, by using an internal connexion clock into the FPGA
    Because the pin clkusr AC13 is not accessible

    Attached my design, for PCI express testing compiled with Quartus pro 22.3

    thanks for your help ..

    regards

    regards

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    3 years ago
    Pin connection guidelines clearly state:

    "This pin is used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers".
    • manu-solystic's avatar
      manu-solystic
      Icon for New Contributor rankNew Contributor
      3 years ago

      So Thanks

      So i saw this item, but too late, on my board, this pin is not connected,

      So i Ask here , if there is a way to route another clock to this signals

      If I can check the PCI express, on my board, without this pin
      We plan to reroute this board, with this clock connected,
      but what i want is to check the PCI express on my prototype board

      regards


    • manu-solystic's avatar
      manu-solystic
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thanks,

      But the AA6 pin if for 484 pin FBGA Cyclone 10 GX
      On my design I have a 672 Pins FBGA , and the AA6 is the TRST signals
      I do not know if it's working on a 672 pins FBGA

      Regards

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    Thanks for your shift response.

    I dont see any other option of clock user other than that.


    Perhaps you can take a try and see if it is workable or not. Let me know your finding.

    Looking forward to hear back from you.


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    We wouldn't advise turning off the CLKUSR clock. In my view the FPGA device won't be expecting this to happen.

    The CYclone 10 PCG states on page 19 :


    Hope this clarified,

    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


    • manu-solystic's avatar
      manu-solystic
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      So I understand that the only solution is to connect a clock on the clkuser pin

      So you can close this ticket

      regards

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    Thanks for your understanding.

    With that said, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel