Cyclone 10GX PCI express without clk_user any solution ?

Hi

Thanks for your answer
So I am using a cyclone 10GX FPGA 10CX085YF672E6G on my design

And i want to test the PCI express on my design
I use the folowing Intel Example

1) - Cyclone 10 GX - PCIe Gen1 x1 Avl-ST

2) - Cyclone 10 GX - CvP Initialization Design Example

Theses design does not work on my board,

Clk_usr (pin AC13) is not connected on my design, and i cannot connect any signals on this pin,

Because this pin is not accessible (no via, or pin_escape to access for this pin)

So I want to know

Do i need the clk_usr for the pci express HIP,
Can I use another clock already connected on my degin

On my design I have a 25Mhz clock, and a 100Mhz Clock,

I ask if there is any way to use pci express without clk_usr, by using an internal connexion clock into the FPGA
Because the pin clkusr AC13 is not accessible

Attached my design, for PCI express testing compiled with Quartus pro 22.3

thanks for your help ..

regards

regards