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Rollo_Tomasi's avatar
Rollo_Tomasi
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone 10 LP FPGA Triple-Speed Ethernet and Intel On-Board PHY Chip Reference Design

Hi,

I tried to follow the instructions in the document (Test Case—Avalon-ST Reverse Loopback's section in particulary), but i don't undestand a lot of things.

First, are we ok that to be done, this design requires a crossover ethernet cable if we want to only usethe C10LP and a computer, right?

Second, in the system consol, i run the following command and i have these results:

% source config.tcl (can be seen in config.tcl results.txt)

% source eth_gen_start.tcl (can be seen in eth_gen_start.tcl results.txt)

% source tse_stat_read.tcl (can be seen in tse_stat_read.tcl results.txt)

The only file i mod was eth_gen_start.tcl. (can be seen in eth_gen_start.tcl mod.txt)

Is this the right method to follow?

Third, I don't understand whyi obtain these follow lines in eth_gen_start.tcl:

Number of packets received OK = 0
Number of packets received error = 1

Does it mean that my loopback doesn't work?

Can someone help me with this Design?

Thank you a lot.

6 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I believe you are referring to instruction in below doc.


    For of all, May I know have you tested with "internal MAC loopback" to ensure your board is working correctly first ? Else I advise you to start with "internal MAC loopback" mode first.


    For "Avalon ST reverse loopback", Pls use the CAT5e cable supplied together in the dev kit box.

    • This mode works in a way that you have an external Ethernet generator/checker test equipment that send Ethernet packet to FPGA Rx, data is then loopback insides FPGA from Rx back to Tx and send back to external Ethernet generator/checker test equipment
    • I noticed you set both source MAC address and destination MAC address to same address which is weird. Byright, source MAC address should be FPGA MAC address while destination MAC address should be your test equipment MAC address
    • Also, pls take note that following setting should be same between FPGA MAC, on board PHY chip and also your test equipment
      • speed = 10M/100M or 1000Mbps ?
      • auto-negotionation = on/off ?
      • full or half duplex setting ?
      • loopback setting = enable/disable ?


    Thanks.


    Regards,

    dlim



    • Rollo_Tomasi's avatar
      Rollo_Tomasi
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi @Deshi_Intel,

      First, thank you for you reply.

      To answer you, yes i have tried "internal MAC loopback" and it works correctly.

      My C10LP did'nt come with a CAT5e cable. I use a crossover ethernet cable with it.

      For the MAC address and destination MAC address, i thin i set it correctly too, but i don't want that my MAC adress appears here, so i remove it.

      I tried to set my test equipment with auto-negotionation, and also with 1000Mbps in Full Duplex.

      But like i said, i have always :

      Number of packets received OK = 0
      Number of packets received error = 1

      Thank you.

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Your log result shown PHY link down with CRC error. Yet, looks like your MAC and PHY setting looks correct.


    I suspect the PHY chip doesn't receive correct data from your external test pattern generator source.

    • I foresee it's either there is some setting issue on your test pattern generator
    • Or the cable that you are using is not working. Could be due to the cross over wiring or the cable itself is bad. You can try out maybe straight through cable or just try another cross over cable.


    I do noticed there are 2 type of wiring mapping in wiki page


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Your log result shown PHY link down with CRC error. Yet, looks like your MAC and PHY setting looks correct.


    I suspect the PHY chip doesn't receive correct data from your external test pattern generator source.

    • I foresee it's either there is some setting issue on your test pattern generator
    • Or the cable that you are using is not working. Could be due to the cross over wiring or the cable itself is bad. You can try out maybe straight through cable or just try another cross over cable.


    I do noticed there are 2 type of wiring mapping in wiki page


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I have not hear back from you for a while.


    Is there any latest update that you want to share with me ?


    Thanks.


    Regards,

    dlim


  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,


    I am closing this case since I never hear back from you.


    Thanks.


    Regards,

    dlim