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Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


I believe you are referring to instruction in below doc.


For of all, May I know have you tested with "internal MAC loopback" to ensure your board is working correctly first ? Else I advise you to start with "internal MAC loopback" mode first.


For "Avalon ST reverse loopback", Pls use the CAT5e cable supplied together in the dev kit box.

  • This mode works in a way that you have an external Ethernet generator/checker test equipment that send Ethernet packet to FPGA Rx, data is then loopback insides FPGA from Rx back to Tx and send back to external Ethernet generator/checker test equipment
  • I noticed you set both source MAC address and destination MAC address to same address which is weird. Byright, source MAC address should be FPGA MAC address while destination MAC address should be your test equipment MAC address
  • Also, pls take note that following setting should be same between FPGA MAC, on board PHY chip and also your test equipment
    • speed = 10M/100M or 1000Mbps ?
    • auto-negotionation = on/off ?
    • full or half duplex setting ?
    • loopback setting = enable/disable ?


Thanks.


Regards,

dlim



  • Rollo_Tomasi's avatar
    Rollo_Tomasi
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi @Deshi_Intel,

    First, thank you for you reply.

    To answer you, yes i have tried "internal MAC loopback" and it works correctly.

    My C10LP did'nt come with a CAT5e cable. I use a crossover ethernet cable with it.

    For the MAC address and destination MAC address, i thin i set it correctly too, but i don't want that my MAC adress appears here, so i remove it.

    I tried to set my test equipment with auto-negotionation, and also with 1000Mbps in Full Duplex.

    But like i said, i have always :

    Number of packets received OK = 0
    Number of packets received error = 1

    Thank you.