Cyclone 10 LP FPGA Triple-Speed Ethernet and Intel On-Board PHY Chip Reference Design

Hi,

Your log result shown PHY link down with CRC error. Yet, looks like your MAC and PHY setting looks correct.

I suspect the PHY chip doesn't receive correct data from your external test pattern generator source.

• I foresee it's either there is some setting issue on your test pattern generator
• Or the cable that you are using is not working. Could be due to the cross over wiring or the cable itself is bad. You can try out maybe straight through cable or just try another cross over cable.

I do noticed there are 2 type of wiring mapping in wiki page

• https://en.wikipedia.org/wiki/Category_5_cable

Thanks.

Regards,

dlim