Custom transceiver PCS/PMA interface width?

Hi,

From transceiver serializer/de-serializer architecture perspective, the max PCS/PMA is 64 bits. There is no way to go beyond that.

My suggestion is you need to post process the data accordingly in FPGA core logic using your own custom IP.

Thanks.

Regards,

dlim

Hi,

Yup, you got it right. It will take 5 times longer to sample all 100 bits.

Are you building custom protocol or follow some industry standard protocol.

Industry standard protocol typically has fixed the transceiver data rate so user can't simply boost the data rate

Thanks.

Regards,

dlim

I am doing a custom interface. When I was testing the 10.4 Gbps with a 64 bit wide PCS/PMA interface, I was clocking the parallel data in at 162.5MHz which gave me the 10.4 Gbps constant stream (I want a constant stream of data). If I will now be running at 10 Gbps with only 20 bit wide PCS/PMA does the transceiver handle clocking the parallel data in at 500 MHz so I can get all 100 bits into the desired 10nS span for a constant stream of data?

HI,

Theoretically make sense if you are able to close FPGA core timing with 500MHz Fmax.

Good luck in stretching the Fmax goal then ! :)

Regards,

dlim

Thank you very much for taking the time to help me understand all this, this is my first foray into multi-gigabit transceivers.

There is one thing I am still confused on if you don't mind explaining or at least pointing me in the right direction so I can learn about it.

If I wasn't trying to allocate every possible bit (5 frames of 20 parallel bits at 500MHz for a 10GHz serial stream of 100 bits every 10nS), what does the transceiver do if I were only sending 2 frames of 20 bits? How do I choose what frequency to clock the 20 parallel lines into the transceiver at? What does the transmitted signal look like in between frames?

Thank you,

Mark

Hi Mark,

Are you trying to confuse yourself and me ? :)

Let's revisit the basic again. Below statement is TRUE regardless of whether there is data traffic or not

1. Configuring transceiver to 10Gbps means that on board transceiver channel will be sending data at 10Gbps (this is purely based on the clock speed to output the data at desired data rate)
2. Intel FPGA transceiver channel has a PMA_PCS width serializer/de-serialzer factor that convert the serial data into parallel data and vice versa
3. The required FPGA core clock frequency to successfully transfer the data over the transceiver channel = transceiver data rate / (PMA_PCS width)

• example 1, XCVR data rate = 10Gbps, (PMA_PCS width) = 32, required FPGA core clock = 10Gbps/32 = 312.5MHz
  • example 2, XCVR data rate = 10Gbps, (PMA_PCS width) = 64, required FPGA core clock = 10Gbps/32 = 156.25MHz
  • This formula has nothing to do with how many data bit that user is trying to send through the transceiver channel.

The transceiver channel is just a physical medium to pass through the data at some desired speed. It doesn't process or manipulate the data. That's the job of user core logic design

1. what does the transceiver do if I were only sending 2 frames of 20 bits ?

• Remember, the transceiver doesn't process the data, it's just a physical medium. User logic design is the one that control/process the data
  • Imagine transceiver is just like a "road" while data is just like a "car" and the car must drive at speed of 100km/hr on the road
  • For instance : yesterday 100 car pass through the road at speed of 100km/hr
  • Today we only have 20 car pass through the road at speed of 100km/hr
  • Can you tell me what's the road going to do to the 20 car ? This is the part that you confused me :)

1. How do I choose what frequency to clock the 20 parallel lines into the transceiver at ?

• Once user configured the transceiver to certain data rate, you just need to follow below formula. This formula doesn't concern user sent how many bits over the transceiver channel
  • FPGA core clock frequency = transceiver data rate / (PMA_PCS width)

1. What does the transmitted signal look like in between frames ?

• Which particular transceiver signal that you are referring to ?
  • If it's data bus then should be zero when there is no data traffic on it

Some of the important notes :

• Transceiver RX channel PMA has a design block called CDR. This CDR will loose lock and caused the transceiver channel link down if there is no data flow for sometime. That's why most of the industry protocol has design requirement to send dummy "IDLE" data traffic when it's not transferring meaningful payload data to keep the transceiver channel alive
• Honestly speaking, unlikely you are able to close FPGA core logic design timing at 500MHz using Cyclone 10 GX FPGA. Pls consider to increase the PMA/PCS width setting to reduce the required FPGA core clock frequency
• Lastly, I encourage you to run NativePHY IP simulation to better understand the transceiver architecture and expected behaviour.

Thanks.

Regards,

dlim

Thank you very much for such a detailed response. It makes much more sense now and you have given me much more insight. You have been very helpful.

Thank you,

Mark

You are welcome ! :0