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MADesigner's avatar
MADesigner
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Custom transceiver PCS/PMA interface width?

I currently have a Cyclone 10 GX and I was testing the XCVR_NativePhy IP and the XCVR_ATXPLL IP. I succeeded in setting up a Basic (Enhanced PCS) transceiver at 10400 Mbps with a 64 bit wide PCS/PMA ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Theoretically make sense if you are able to close FPGA core timing with 500MHz Fmax.

Good luck in stretching the Fmax goal then ! :)

Regards,

dlim