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MADesigner's avatar
MADesigner
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Custom transceiver PCS/PMA interface width?

I currently have a Cyclone 10 GX and I was testing the XCVR_NativePhy IP and the XCVR_ATXPLL IP. I succeeded in setting up a Basic (Enhanced PCS) transceiver at 10400 Mbps with a 64 bit wide PCS/PMA ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

From transceiver serializer/de-serializer architecture perspective, the max PCS/PMA is 64 bits. There is no way to go beyond that.

My suggestion is you need to post process the data accordingly in FPGA core logic using your own custom IP.

Thanks.

Regards,

dlim

MADesigner's avatar
MADesigner
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thank you very much for responding!

That is what I was afraid of. Are you suggesting that I maybe use a 20 bit wide interface and then some type of state machine to step through all 100 bits of my desired data packet? Would it then take 5 times as long to send the same data or would I simply have to step through the state machine 5 times faster to supply the transceiver with the data at the desired rate?